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DRA821U4...ALM 数据表(PDF) 97 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 97 Page - Texas Instruments

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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
(1)
NOM
MAX
(1)
UNIT
VDDA_MCU_PLLGRP0
Analog supply for MCU PLL Group 0
1.71
1.8
1.89
V
VDDA_PLLGRP0
Analog supply for MAIN PLL Group 0
1.71
1.8
1.89
V
VDDA_PLLGRP4
Analog supply for MAIN PLL Group 4
1.71
1.8
1.89
V
VDDA_PLLGRP6
Analog supply for MAIN PLL Group 6
1.71
1.8
1.89
V
VDDA_PLLGRP8
Analog supply for MAIN PLL Group 8
1.71
1.8
1.89
V
VDDA_WKUP
Oscillator supply for WKUP domain
1.71
1.8
1.89
V
VDDA_ADC_MCU
ADC analog supply
1.71
1.8
1.89
V
VDDA_0P8_PLL_DDR
DDR PLL analog supply
0.76
0.8
0.84
V
VDDA_MCU_TEMP
Analog supply for temperature sensor 0 in MCU
domain
1.71
1.8
1.89
V
VDDA_POR_WKUP
WKUP domain analog supply
1.71
1.8
1.89
V
VDDA_TEMP0
Analog supply for temperature sensor 0
1.71
1.8
1.89
V
VDDA_TEMP1
Analog supply for temperature sensor 1
1.71
1.8
1.89
V
VDDS_DDR(2)
DDR inteface power supply
1.05
1.1
1.15
V
VDDS_DDR_BIAS(2)
Bias supply for LPDDR4
1.05
1.1
1.15
V
VDDS_DDR_C(2)
IO power for DDR Memory Clock Bit (MCB) macro
1.05
1.1
1.15
V
VDDS_MMC0
MMC0 IO supply
1.71
1.8
1.89
V
VDDA_OSC1
HFOSC1 supply
1.71
1.8
1.89
V
VDDA_*
Peak to Peak Noise for all VDDA inputs
25
mV
VDDSHV0
IO supply for main domain
general
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV0_MCU
IO supply MCUSS general IO
group, and MCU and Main
domain warm reset pins
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV1_MCU
IO supply for MCUSS IO group 1 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV2
IO supply for main domain IO
group 2
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV2_MCU
IO supply for MCUSS IO group 2 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV5
IO supply for main domain IO
group 5
1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
USB0_VBUS
Voltage range for USB VBUS comparator input
0
See(6)
3.46
V
USB0_ID
Voltage range for the USB ID input
See(4)
V
VSS
Ground
0
V
TJ
Operating junction temperature
range
Automotive
-40
125
°C
Extended
-40
105
°C
Commercial
0
90
°C
(1)
The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.
(2)
A single 1.1-V source must drive all three VDDS_DDR, VDDS_DDR_BIAS, VDDS_DDR_C supplies. These supplies are required to
still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.
(3)
A single 0.8-V source must drive the VDD_CORE and VDDA_0P8_ PHY input supplies. Also, include Analog filter components on the
individual VDDA_0P8_ PHY input supplies for interfaces that are used in the system.
(4)
This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should
be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any
external voltage source.
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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