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DRA821U4...ALM 数据表(PDF) 9 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 9 Page - Texas Instruments |
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9 / 252 page ![]() Table 5-1. Device Comparison (continued) Same table as the unhidden one. Done to remove columns A4 and A2 FEATURES REFERENCE NAME DRA821U4 DRA821U2 Enhanced Capture Module ECAP 3 3 Enhanced Quadrature Encoder Pulse Module EQEP 3 3 Universal Asynchronous Receiver and Transmitter UART 12 12 Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY USB Yes(1) Yes(1) (1) SGMII, USB3.0, and PCIE share total of four SerDes lanes. (2) DRA821U4 CPSW5G supports the following instances, signals, and modes of operation: • PORT1 Signals: RMII1/RGMII1/SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII • PORT2 Signals: RMII2/RGMII2/SGMII2, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII • PORT3 Signals: RMII3/RGMII3/SGMII3, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII • PORT4 Signals: RMII4/RGMII4/SGMII4, Modes: One of 2.5 Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII, 5Gb QSGMII • QSGMII mode combines all four internal ports of the CPSW onto a single SERDES lane. Each port in this mode operates at 1-Gb full duplex – Any one of the port signals SGMII1:4 can be selected for this SERDES connectivity where upon the non-selected signals are unused by the CPSW DRA821U2 CPSW5G supports the following instances, signals, and modes of operation: • PORT1 Signals: RMII1/RGMII1/SGMII1, Modes: One of 5Gb, 10Gb USXGMII/XFI, 2.5Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII • PORT2 Signals: RMII2/RGMII2/SGMII2, Modes: One of 2.5Gb SGMII/XAUI, 1Gb SGMII, 1Gb RGMII, 100Mb RMII • PORT3 and PORT4 and corresponding signals are not supported • QSGMII mode is not supported (3) CPSW2G supports the following instances, signals, and modes of operation: • PORT1 Signals: MCU_RMII1/MCU_RGMII1, Modes: One of 1Gb RGMII, 100Mb RMII (4) Flash interface can be configured as OSPI0, or HyperBus. (5) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y) identifier in the Section 10.1.2, Nomenclature Description Table. (6) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Section 10.1.2, Nomenclature Description table. (7) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Section 10.1.2, Nomenclature Description table. (8) Two ports are internally connected only. Not connected to any pins. 5.1 Related Products Companion Products for DRA821U Review products that are frequently purchased or used in conjunction with this product. Software Development Kit for DRA821 Jacinto™ Processors Processor SDK RTOS (PSDK RTOS) can be used together with Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX), to form a multi-processor software development platform for DRA821 SoCs within the TI’s Jacinto™ Processors platform. The SDK provides a comprehensive set of software tools and components to help users develop and deploy their applications on supported J7 SoCs. PSDK RTOS and either PSDK Linux or PSDK QNX can be used together to implement various use-cases in factory and building automation, and gateway systems. DRA821 Evaluation Module The J700XSOMXEVM paired with the J721EXCP01EVM Common Processor Board is an evaluation platform designed to speed up development efforts and reduce time to market for networking applications throughout automotive and industrial markets. The EVM is supported by Processor SDK, which includes foundational drivers, compute and vision kernels, and example application frameworks and demonstrations that show you how to take advantage of the powerful, heterogeneous architecture of Jacinto 7 processors. Application Notes and White Paper Gateway application processor with integrated system MCU. www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRA821U-Q1 |
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