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DRA821U4...ALM 数据表(PDF) 35 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 35 Page - Texas Instruments |
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35 / 252 page ![]() Table 6-1. Pin Attributes (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUX MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. MUX MODE [7] I/O VOLTAGE VALUE [8] POWER [9] HYS [10] BUFFER TYPE [11] PULL UP/DOWN TYPE [12] DSIS [13] RX ACTIVE/ TX DISABLE [14] IO RET [15] W8 SERDES0_RX1_N SERDES0_RX1_N I 0.8 V VDDA_0P8_SERDES0 , VDDA_1P8_SERDES0 , VDDA_0P8_SERDES0 _C SERDES SGMII4_RX0_N I PCIE1_RX1_N I USB0_SSRX2N I W9 SERDES0_RX1_P SERDES0_RX1_P I 0.8 V VDDA_0P8_SERDES0 , VDDA_1P8_SERDES0 , VDDA_0P8_SERDES0 _C SERDES SGMII4_RX0_P I PCIE1_RX1_P I USB0_SSRX2P I Y7 SERDES0_RX2_N SERDES0_RX2_N I 0.8 V VDDA_0P8_SERDES0 , VDDA_1P8_SERDES0 , VDDA_0P8_SERDES0 _C SERDES SGMII1_RX0_N I PCIE1_RX2_N I USB0_SSRX1N I Y8 SERDES0_RX2_P SERDES0_RX2_P I 0.8 V VDDA_0P8_SERDES0 , VDDA_1P8_SERDES0 , VDDA_0P8_SERDES0 _C SERDES SGMII1_RX0_P I PCIE1_RX2_P I USB0_SSRX1P I W5 SERDES0_RX3_N SERDES0_RX3_N I 0.8 V VDDA_0P8_SERDES0 , VDDA_1P8_SERDES0 , VDDA_0P8_SERDES0 _C SERDES SGMII2_RX0_N I PCIE1_RX3_N I USB0_SSRX2N I www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRA821U-Q1 |
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