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DRA821U4...ALM 数据表(PDF) 49 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 49 Page - Texas Instruments

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6.3.2 DDRSS
6.3.2.1 MAIN Domain
Table 6-3. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN TYPE
[3]
BALL [4]
DDR_RET
External IO Retention Enable
I
R5
DDR0_CKN
DDRSS Differential Clock (negative)
IO
H1
DDR0_CKP
DDRSS Differential Clock (positive)
IO
G1
DDR0_RESETn
DDRSS Reset
IO
J5
DDR0_CA0
DDRSS Command Address
IO
G4
DDR0_CA1
DDRSS Command Address
IO
H3
DDR0_CA2
DDRSS Command Address
IO
J4
DDR0_CA3
DDRSS Command Address
IO
K1
DDR0_CA4
DDRSS Command Address
IO
J2
DDR0_CA5
DDRSS Command Address
IO
H5
DDR0_CAL0
(1)
IO Pad Calibration Resistor
A
K5
DDR0_CKE0
DDRSS Clock Enable
IO
G2
DDR0_CKE1
DDRSS Clock Enable
IO
H2
DDR0_CSn0_0
DDRSS Chip Select
IO
G3
DDR0_CSn0_1
DDRSS Chip Select
IO
K2
DDR0_CSn1_0
DDRSS Chip Select
IO
G5
DDR0_CSn1_1
DDRSS Chip Select
IO
J3
DDR0_DM0
DDRSS Data Mask
IO
A3
DDR0_DM1
DDRSS Data Mask
IO
E4
DDR0_DM2
DDRSS Data Mask
IO
N1
DDR0_DM3
DDRSS Data Mask
IO
R4
DDR0_DQ0
DDRSS Data
IO
B4
DDR0_DQ1
DDRSS Data
IO
A4
DDR0_DQ2
DDRSS Data
IO
C4
DDR0_DQ3
DDRSS Data
IO
C1
DDR0_DQ4
DDRSS Data
IO
C3
DDR0_DQ5
DDRSS Data
IO
C2
DDR0_DQ6
DDRSS Data
IO
A2
DDR0_DQ7
DDRSS Data
IO
B3
DDR0_DQ8
DDRSS Data
IO
D1
DDR0_DQ9
DDRSS Data
IO
D2
DDR0_DQ10
DDRSS Data
IO
F2
DDR0_DQ11
DDRSS Data
IO
E3
DDR0_DQ12
DDRSS Data
IO
F3
DDR0_DQ13
DDRSS Data
IO
F4
DDR0_DQ14
DDRSS Data
IO
D4
DDR0_DQ15
DDRSS Data
IO
F5
DDR0_DQ16
DDRSS Data
IO
K4
DDR0_DQ17
DDRSS Data
IO
L4
DDR0_DQ18
DDRSS Data
IO
M4
DDR0_DQ19
DDRSS Data
IO
L3
DDR0_DQ20
DDRSS Data
IO
L2
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DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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