DRA821U4...ALM datasheet(5/252 Pages) TI

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4 Revision History

Changes from December 17, 2021 to December 16, 2022 (from Revision C (December 2021) to

Revision D (December 2022))

Page

• Global: Changed the document product status from Advance Information (AI) to Production Mixed Status",

where the document content includes both "Production Data" and preproduction (AI) information, noted as

preproduction, Advance Information (AI), or preview......................................................................................... 1

• Global: The Device Type field description in the Device Naming Convention section, has preproduction (AI)

information, noted as preproduction, Advance Information (AI), or preview.......................................................1

• (Features): Added clarification to the "Supports LPDDR4 memory types …" sub-bullet....................................1

• (Device Information): Updated/Changed the table title to "Package Information" plus, added additional part

numbers..............................................................................................................................................................2

• (Device Comparison): Updated/Changed the General-Purpose I/O (GPIO) from "Up to 127" to "Up to 141" for

both GPNs: DRA821U4 and DRA821U2............................................................................................................8

• (Device Comparison): Added a QSGMII mode of operation under the "DRA821U4 CPSW5G supports …".....8

• (Power Supply): Added "±10%" to the "This pin must always be connected …" footnote................................ 79

• (Connections for Unused Pins): Deleted Notes on VMON balls and MMC1_SDCD........................................ 91

• (Specifications): Deleted lead-in Note.............................................................................................................. 94

• (Abs Max Ratings): Added Latch-up Performance, Class II (125°C) row and associated footnote..................94

• (Absolute Maximum Ratings): Updated the "Operation outside the Absolute Maximum Ratings may cause …"

disclaimer footnote............................................................................................................................................94

• (Recommended Operating Conditions): Added a footnote indicating a single 0.8-V source must drive all four

VDDA_CORE, VDDA_0P8_SERDES0, VDDA_0P8_SERDES0_C, and VDDA_0P8_USB supplies............. 96

• (Power Consumption Summary): Deleted section............................................................................................98

• (I2C OD FS Electrical Characteristics): Updated /Changed I(OL) from "3" to "10" mA.................................... 99

• (ADC12BT Electrical Characteristics): Updated/Changed DNL, Differential Non-Linearity MAX value from "2"

to "4" LSB....................................................................................................................................................... 102

• (ADC12BT Electrical Characteristics): Updated/Changed INL, Integral Non-Linearity MAX value from "±3" to

"±4" LSB..........................................................................................................................................................102

• Timing and Switching Characteristics): Updated/Changed Note on valid timings from SLEWRATE to

DVR_STR (Drvie Strength) control discussion............................................................................................... 108

• (Power Supply Sequencing): Updated/Changed Power Up and Down images for all domains

[OSC1_XO(optional) and WKUP_OSC_XO].................................................................................................. 109

• (Power Supply Sequencing): Deleted the "All power sequence timing shown …" Note.................................109

• (Combined MCU and Main Domains Power- Up Sequencing): Deleted duplicate bullets from the Terminology

textnote under figure....................................................................................................................................... 110

• (Entry and Exit of MCU Only State): Added missing sentence content for end of paragraph.........................118

• (System Timing): Added section (new)........................................................................................................... 122

• (Reset Timing): Updated/Changed section including Timing Requirements tables, associated figures, addition

of footnotes/notes........................................................................................................................................... 122

• (Safety Signal Timing): Added new section.................................................................................................... 130

• (CPSW2G): Added "PCB CONNECTIVITY REQUIREMENTS" parametric information to the CPSW2G Timing

Conditions table.............................................................................................................................................. 146

• (Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode): Updated/Changed the

RMII6 Delay Time MAX values from "13" to "10" ns.......................................................................................147

• (CPSW5G): Added "PCB CONNECTIVITY REQUIREMENTS" parametric information to the CPSW5G Timing

Conditions table.............................................................................................................................................. 150

• (CPSW5G MDIO Interface Timings): Added CPSW5G MDIO Timing Conditions table ................................ 151

• (Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode): Updated/Changed the

RMII6 Delay Time MAX values from "13" to "10" ns.......................................................................................153

• (DDRSS): Added an additional bullet the "… LPDDR4 SDRAM devices with the following features:" list..... 155

• Updated min values for Timing Requirements for EPWM table......................................................................157

• (GPIO Timing Conditions): Updated/Changed Input Conditions and Timing Requirements tables to reflect

current.............................................................................................................................................................160

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DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

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