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DRA821U4...ALM 数据表(PDF) 78 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 78 Page - Texas Instruments |
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78 / 252 page  Table 6-99. Clock1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OSC1_XO High frequency oscillator output O J19 6.3.25.2.2 WKUP Domain Table 6-100. Clock0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_LF_CLKIN Low frequency (32.768 KHz) oscillator input I C17 WKUP_OSC0_XI High frequency oscillator input I K21 WKUP_OSC0_XO High frequency oscillator output O L21 6.3.25.3 System 6.3.25.3.1 MAIN Domain Table 6-101. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] AUDIO_EXT_REFCLK0 External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP IO V18 AUDIO_EXT_REFCLK1 External clock routed to ATL or McASP as one of the selectable input clock sources, or as a output clock output for ATL or McASP IO U21 EXTINTn External Interrupt I U6 EXT_REFCLK1 External clock input to Main Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) I T3 GPMC0_FCLK_MUX GPMC functional clock output selected through a mux logic O V14 OBSCLK0 Observation clock output for test and debug purposes only O W1 OBSCLK1 Observation clock output for test and debug purposes only O V16 OBSCLK2 Observation clock output for test and debug purposes only O V14 RESETSTATz Main Domain warm reset status output O U2 SOC_SAFETY_ERRORn Error signal output from Main Domain ESM IO V2 SYNC0_OUT CPTS Time Stamp Generator Bit 0 O U3 SYNC1_OUT CPTS Time Stamp Generator Bit 1 O T3 SYNC2_OUT CPTS Time Stamp Generator Bit 2 O W16 SYNC3_OUT CPTS Time Stamp Generator Bit 3 O V21 SYSCLKOUT0 SYSCLK0 output from Main PLL controller (divided by 6) for test and debug purposes only O V1 6.3.25.3.2 WKUP Domain Table 6-102. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_CLKOUT0 Reference clock output for Ethernet PHYs (50MHz or 25MHz) OZ C16 MCU_EXT_REFCLK0 External system clock input I C20, E18 DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 78 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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