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DRA821U4...ALM 数据表(PDF) 98 Page - Texas Instruments |
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DRA821U4...ALM 数据表(HTML) 98 Page - Texas Instruments |
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98 / 252 page  (5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry. (6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.3, USB VBUS Design Guidelines 7.4 Power-On-Hours (POH) IP1 2 3 VOLTAGE DOMAIN VOLTAGE (V) (MAX) FREQUENCY (MHz) (MAX) Tj(°C) POH All 100% All All Supported OPPs Automotive -40°C to 125°C 20000 All 100% All All Supported OPPs Extended -40°C to 105°C 100000 All 100% All All Supported OPPs Commercial 0°C to 90°C 100000 1. This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. 2. Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures. 3. POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH. 4. Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C, and 10%@125°C. 7.5 Operating Performance Points This section describes the operating conditions of the device. This section also contains the description of each Operating Performance Point (OPP) for processor clocks and device core clocks. Table 7-1 describes the maximum supported frequency per speed grade for the device. Table 7-1. Speed Grade Maximum Frequency DEVICE MAXIMUM FREQUENCY (MHz) A72SS0 R5FSS0 MCU_R5FSS0 CBASS0 DMSC LPDDR4 (1) DRA821xT 2000 1000 1000 500 333 1600 (DDR-3200) DRA821xL 1500 1000 1000 500 333 1600 (DDR-3200) DRA821xE 1000 1000 1000 500 333 1600 (DDR-3200) DRA821xC 750 500 1000 500 333 1600 (DDR-3200) (1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill, PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout Guidelines for details. DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 98 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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