HC705JB2GRSSLASHH datasheet(13/128 Pages) NXP

13 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

GENERAL DESCRIPTION

REV 1.1

1-1

SECTION 1

GENERAL DESCRIPTION

The MC68HC705JB2 is a member of the low-cost, high-performance MC68HC05

Family of 8-bit microcontroller units (MCUs). The MC68HC05 Family is based on

the Customer-Speciﬁed Integrated Circuit (CSIC) design strategy. All MCUs in the

family use the popular MC68HC05 central processing unit (CPU) and are

available with a variety of subsystems, memory sizes and types, and package

types. The MC68HC705JB2 is speciﬁcally designed to be used in applications

where a Universal Serial Bus (USB) interface is required.

1.1

FEATURES

•

Industry standard M68HC05 CPU core

•

Memory-mapped Input/Output (I/O) registers

•

2048 Bytes of user EPROM

•

128 Bytes of user RAM

•

Fully compliant Low Speed USB with 3 Endpoints:

– 1 Control Endpoint (2 x 8-byte buffer)

– 2 Interrupt Endpoints (1 x 8-byte buffer shared)

•

3.3Volt dc output pin for USB pullup resistors

•

Multi-Function Timer

•

16-Bit Input Capture/Output Compare Timer

•

11 Bidirectional I/O pins with the following features:

– 9 I/Os have software programmable pull-down capability

– 2 open-drain I/Os have software programmable pull-up, 25mA current

sink capability

– 4 I/Os with external interrupt capability

•

Low Voltage Reset (LVR) circuit

•

Power saving STOP and WAIT Modes

•

Available in 20-Pin PDIP and 20-pin SOIC packages

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H 数据表(PDF) 13 Page - NXP Semiconductors

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