HC705JB2GRSSLASHH datasheet(90/128 Pages) NXP

90 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

UNIVERSAL SERIAL BUS MODULE

MC68HC705JB2

10-22

REV 1.1

EOPFR — End of Packet Flag Reset

Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a

logic 0 to the EOPFR has no effect. Reset clears this bit.

10.5.4 USB Control Register 0 (UCR0)

T0SEQ — Endpoint 0 Transmit Sequence Bit

This read/write bit determines which type of data packet (DATA0 or DATA1) will

be sent during the next IN transaction. Toggling of this bit must be controlled by

software. Reset clears this bit.

1 =

DATA1 Token active for next Endpoint 0 transmit

0 =

DATA0 Token active for next Endpoint 0 transmit

STALL0 — Endpoint 0 Force Stall Bit

This read/write bit causes Endpoint 0 to return a STALL handshake when

polled by either an IN or OUT token by the USB Host Controller. The USB

hardware clears this bit when a SETUP token is received. Reset clears this bit.

1 =

Send STALL handshake

0 =

Default

TX0E — Endpoint 0 Transmit Enable

This read/write bit enables a transmit to occur when the USB Host controller

sends an IN token to Endpoint 0. Software should set this bit when data is

ready to be transmitted. It must be cleared by software when no more Endpoint

0 data needs to be transmitted.

If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake

to any Endpoint 0 IN tokens. Reset clears this bit.

1 =

Data is ready to be sent.

0 =

Data is not ready. Respond with NAK.

RX0E — Endpoint 0 Receive Enable

This read/write bit enables a receive to occur when the USB Host controller

sends an OUT token to Endpoint 0. Software should set this bit when data is

ready to be received. It must be cleared by software when data cannot be

received.

If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake

to any Endpoint 0 OUT tokens. Reset clears this bit.

1 =

Data is ready to be received.

0 =

Not ready for data. Respond with NAK.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UCR0

T0SEQ

STALL0

TX0E

RX0E

TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0

$003B

reset

⇒

00000000

Figure 10-23. USB Control Register 0 (UCR0)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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