HC705JB2GRSSLASHH datasheet(75/128 Pages) NXP

75 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

UNIVERSAL SERIAL BUS MODULE

REV 1.1

10-7

Figure 10-7. CRC Block Diagram for Data Packets

10.2.1.6 End Of Packet (EOP)

The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The

single-ended 0 state is indicated by both D+ and D- being below 0.8 V. EOP will be

signaled by driving D+ and D- to the single-ended 0 state for two bit times followed

by driving the lines to the idle state for one bit time. The transition from the single-

ended 0 to the idle state deﬁnes the end of the packet. The idle state is asserted

for one bit time and then both the D+ and D- output drivers are placed in their

high-impedance state. The bus termination resistors hold the bus in the idle state.

Figure 10-8 shows the data signaling and voltage levels for an end of packet

transaction.

MUX

next bit

Input / Output

Update every bit time

Reset to ones at SOP

Equal?

Good CRC

Bad CRC

Expected Residual:

Generator Polynomial:

Data Stream

Output

Data Stream

CRC16 Transmitted

MSB first after final

data byte.

TRANSMIT

RECEIVE

00000

10000

0 001 0 1

00 0 0 0

1 0 000

0 0 110 1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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