HC705JB2GRSSLASHH datasheet(93/128 Pages) NXP

93 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

UNIVERSAL SERIAL BUS MODULE

REV 1.1

10-25

STALL1 — Endpoint 1 Force Stall Bit

This read/write bit causes Endpoint 1 to return a STALL handshake when

polled by either an IN or OUT token by the USB Host Controller. Reset clears

this bit.

1 =

Send STALL handshake

0 =

Default

10.5.7 USB Status Register (USR)

RSEQ — Endpoint 0 Receive Sequence Bit

This read only bit indicates the type of data packet last received for Endpoint 0

(DATA0 or DATA1).

1 =

DATA1 Token received in last Endpoint 0 receive

0 =

DATA0 Token received in last Endpoint 0 receive

SETUP — SETUP Token Detect Bit

This read only bit indicates that a valid SETUP token has been received.

1 =

Last token received for Endpoint 0 was a SETUP token

0 =

Last token received for Endpoint 0 was not a SETUP token

RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet Size

These read only bits store the number of data bytes received for the last OUT

or SETUP transaction for Endpoint 0. These bits are not affected by reset.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

USR

RSEQ

SETUP

RPSIZ3

RPSIZ2

RPSIZ1

RPSIZ0

$003D

reset

⇒

UUUUUUUU

= Unimplemented

Figure 10-26. USB Status Register (USR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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