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HC705JB2GRS/H 数据表(PDF) 86 Page - NXP Semiconductors |
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HC705JB2GRS/H 数据表(HTML) 86 Page - NXP Semiconductors |
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86 / 128 page  GENERAL RELEASE SPECIFICATION August 28, 1998 UNIVERSAL SERIAL BUS MODULE MC68HC705JB2 10-18 REV 1.1 10.5 I/O REGISTER DESCRIPTION The USB Endpoint registers are comprised of a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the USB and the CPU. These registers are shown in Table 10-2. Table 10-2. Register Summary Register Name Bit 7 6 5 4 3 2 1 Bit 0 Addr USB Control Register 2 (UCR2) 0 TX1ST 0 ENABLE2 ENABLE1 STALL2 STALL1 $0037 TX1STR USB Address Register (UADDR) USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 $0038 USB Interrupt Register 0 (UIR0) TXD0F RXD0F RSTF SUSPND TXD0IE RXD0IE 00 $0039 TXD0FR RXD0FR USB Interrupt Register 1 (UIR1) TXD1F EOPF RESUMF 0 TXD1IE EOPIE 00 $003A RESUMFR TXD1FR EOPFR USB Control Register 0 (UCR0) T0SEQ STALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B USB Control Register 1 (UCR1) T1SEQ ENDADD TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C USB Status Register (USR) RSEQ SETUP 0 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 $003D USB Endpoint 0 Data Register 0 (UE0D0) UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0020 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 ↓↓ USB Endpoint 0 Data Register 7 (UE0D7) UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0027 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 USB Endpoint 1/2 Data Register 0 (UE1D0) $0028 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 ↓↓ USB Endpoint 1/2 Data Register 7 (UE1D7) $002F UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 = Unimplemented Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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