HC705JB2GRSSLASHH datasheet(76/128 Pages) NXP

76 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

UNIVERSAL SERIAL BUS MODULE

MC68HC705JB2

10-8

REV 1.1

Figure 10-8. EOP Transaction Voltage Levels

The width of the SE0 in the EOP is about two bit times. The EOP width is

measured with the same capacitive load used for maximum rise and fall times and

is measured at the same level as the differential signal crossover points of the

data lines.

Figure 10-9. EOP Width Timing

10.2.2 Reset Signaling

A reset is signaled on the bus by the presence of an extended SE0 at the USB

data pins of a device. The reset signaling is speciﬁed to be present for a minimum

of 10 ms. An active device (powered and not in the suspend state) seeing a

single-ended zero on its USB data inputs for more than 2.5

µs may treat that signal

as a reset, but must have interpreted the signaling as a reset within 5.5

µs. For a

Low speed device, an SE0 condition between 4 and 8 low speed bit times

represents a valid USB reset.

A USB sourced reset will hold the MC68HC705JB2 in reset for the duration of the

reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be

set after the internal reset is removed (See Section 10.5.2 for more detail).

BUS DRIVEN TO

LAST BIT OF

BUS IDLE

EOP

STROBE

PACKET

IDLE STATE

BUS FLOATS

VOH (min)

VSE (max)

VSE (min)

VOL (min)

VSS

EOP

WIDTH

tPeriod

DIFFERENTIAL

DATA LINES

DATA

CROSSOVER

LEVEL

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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