HC705JB2GRSSLASHH datasheet(3/128 Pages) NXP

3 / 128 page

TABLE OF CONTENTS

Section

Title

Page

August 28, 1998

GENERAL RELEASE SPECIFICATION

REV 1.1

SECTION 1

GENERAL DESCRIPTION

1.1

FEATURES ...................................................................................................... 1-1

1.2

MASK OPTIONS.............................................................................................. 1-2

1.3

MCU STRUCTURE.......................................................................................... 1-3

1.4

FUNCTIONAL PIN DESCRIPTIONS ............................................................... 1-4

1.4.1

VDD, VSS .................................................................................................... 1-4

1.4.2

OSC1, OSC2 ............................................................................................... 1-4

1.4.3

RESET......................................................................................................... 1-6

1.4.4

IRQ/VPP ...................................................................................................... 1-6

1.4.5

PA0-PA7 ...................................................................................................... 1-7

1.4.6

PB0-PB2 ...................................................................................................... 1-7

1.4.7

D+, D– ......................................................................................................... 1-7

1.4.8

3.3V ............................................................................................................. 1-7

SECTION 2

MEMORY

2.1

MEMORY MAP ................................................................................................ 2-1

2.2

I/O AND CONTROL REGISTERS ................................................................... 2-2

2.3

RAM ................................................................................................................. 2-3

2.4

EPROM ............................................................................................................ 2-3

2.5

BOOTLOADER ROM....................................................................................... 2-3

SECTION 3

CENTRAL PROCESSING UNIT

3.1

REGISTERS .................................................................................................... 3-1

3.2

ACCUMULATOR (A)........................................................................................ 3-2

3.3

INDEX REGISTER (X) ..................................................................................... 3-2

3.4

STACK POINTER (SP) .................................................................................... 3-2

3.5

PROGRAM COUNTER (PC) ........................................................................... 3-3

3.6

CONDITION CODE REGISTER (CCR) ........................................................... 3-3

3.6.1

Half Carry Bit (H-Bit) .................................................................................... 3-3

3.6.2

Interrupt Mask (I-Bit) .................................................................................... 3-3

3.6.3

Negative Bit (N-Bit) ...................................................................................... 3-3

3.6.4

Zero Bit (Z-Bit) ............................................................................................. 3-4

3.6.5

Carry/Borrow Bit (C-Bit) ............................................................................... 3-4

SECTION 4

INTERRUPTS

4.1

CPU INTERRUPT PROCESSING ................................................................... 4-1

4.2

RESET INTERRUPT SEQUENCE .................................................................. 4-2

4.3

SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4

4.4

HARDWARE INTERRUPTS ............................................................................ 4-4

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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