HC705JB2GRSSLASHH datasheet(61/128 Pages) NXP

61 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

PROGRAMMABLE TIMER

REV 1.1

9-3

The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations

which contain the current high and low bytes of the 16-bit free-running counter.

Writing to the timer registers has no effect. Reset of the device presets the timer

counter to $FFFC.

The TMRL latch is a transparent read of the LSB until the a read of the TMRH

takes place. A read of the TMRH latches the LSB into the TMRL location until the

TMRL is again read. The latched value remains ﬁxed even if multiple reads of the

TMRH take place before the next read of the TMRL. Therefore, when reading the

MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to

complete the read sequence.

During power-on-reset (POR), the counter is initialized to $FFFC and begins

counting after the oscillator start-up delay. Because the counter is sixteen bits and

preceded by a ﬁxed divide-by-four prescaler, the value in the counter repeats

every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).

When the free-running counter rolls over from $FFFF to $0000, the timer overﬂow

ﬂag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if

the timer overﬂow interrupt enable bit (TOIE) is also set in the TCR. The TOF ﬂag

bit can only be reset by reading the TMRL after reading the TSR.

Other than clearing any possible TOF ﬂags, reading the TMRH and TMRL in any

order or any number of times does not have any effect on the 16-bit free-running

counter.

NOTE

To prevent interrupts from occurring between readings of the TMRH

and TMRL, set the I bit in the condition code register (CCR) before

reading TMRH and clear the I bit after reading TMRL.

9.2

ALTERNATE COUNTER REGISTERS (ACRH, ACRL)

The functional block diagram of the 16-bit free-running timer counter and alternate

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TMRH

TMRH7

TMRH6

TMRH5

TMRH4

TMRH3

TMRH2

TMRH1

TMRH0

$0018

reset:

11111111

TMRL

TMRL7

TMRL6

TMRL5

TMRL4

TMRL3

TMRL2

TMRL1

TMRL0

$0019

reset:

11111100

Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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