HC705JB2GRSSLASHH datasheet(82/128 Pages) NXP

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GENERAL RELEASE SPECIFICATION

August 28, 1998

UNIVERSAL SERIAL BUS MODULE

MC68HC705JB2

10-14

REV 1.1

10.4.3.2 Data Source Jitter

The source of data can have some variation (jitter) in the timing of edges of the

data transmitted. The time between any set of data transitions is N * TPERIOD ±

jitter time, where ‘N’ is the number of bits between the transitions and TPERIOD is

deﬁned as the actual period of the data rate. The data jitter is measured with the

same capacitive load used for maximum rise and fall times and is measured at the

crossover points of the data lines as shown in Figure 10-14.

Figure 10-14. Data Jitter

For low speed transmissions, the jitter time for any consecutive differential data

transitions must be within

±25 ns and within ±10 ns for any set of paired

differential data transitions. These jitter numbers include timing variations due to

differential buffer delay, rise/fall time mismatches, internal clock source jitter, and

to noise and other random effects.

10.4.3.3 Data Signal Rise and Fall Time

The output rise time and fall time are measured between 10% and 90% of the

signal. Edge transition time for the rising and falling edges of low speed signals is

75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into a

capacitive load of 350 pF. The rising and falling edges should be smooth

transitional (monotonic) when driving the cable to avoid excessive EMI.

Figure 10-15. Data Signal Rise and Fall Time

CONSECUTIVE

TRANSITIONS

tPeriod

DIFFERENTIAL

DATA LINES

CROSSOVER

POINTS

PAIRED

TRANSITIONS

DIFFERENTIAL

DATA LINES

RISE TIME

FALL TIME

10%

90%

10%

LOW SPEED: 75ns at CL = 50pF, 300ns at CL = 350pF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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