HC705JB2GRSSLASHH datasheet(9/128 Pages) NXP

9 / 128 page

LIST OF FIGURES

Figure

Title

Page

August 28, 1998

GENERAL RELEASE SPECIFICATION

REV 1.1

vii

1-1

MC68HC705JB2 Block Diagram...................................................................... 1-3

1-2

Pin Assignments for 20-Pin Package............................................................... 1-4

1-3

Oscillator Connections ..................................................................................... 1-5

2-1

MC68HC705JB2 Memory Map ........................................................................ 2-1

2-2

I/O Registers .................................................................................................... 2-2

2-3

I/O Registers $0000-$000F.............................................................................. 2-4

2-4

I/O Registers $0010-$001F.............................................................................. 2-5

2-5

I/O Registers $0020-$003F.............................................................................. 2-6

2-6

Mask Option Register $01FF ........................................................................... 2-6

3-1

MC68HC05 Programming Model ..................................................................... 3-1

4-1

Interrupt Processing Flowchart ........................................................................ 4-3

4-2

External Interrupt (IRQ) Logic .......................................................................... 4-4

4-3

IRQ Control and Status Register (ICSR)......................................................... 4-5

5-1

Reset Block Diagram ....................................................................................... 5-1

6-1

STOP/WAIT Flowchart..................................................................................... 6-2

7-1

Port A I/O Circuitry ........................................................................................... 7-2

7-2

Port B I/O Circuitry ........................................................................................... 7-4

7-3

Port B Data Direction Register ......................................................................... 7-5

8-1

Multi-Function Timer Block Diagram ................................................................ 8-1

8-2

Timer Counter Register.................................................................................... 8-2

8-3

Timer Control/Status Register (TCSR)............................................................. 8-3

9-1

Programmable Timer Block Diagram ............................................................... 9-1

9-2

Programmable Timer Counter Block Diagram ................................................. 9-2

9-3

Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3

9-4

Alternate Counter Block Diagram..................................................................... 9-4

9-5

Alternate Counter Registers (ACRH, ACRL).................................................... 9-4

9-6

Timer Input Capture Block Diagram................................................................. 9-5

9-7

Input Capture Registers (ICRH, ICRL)............................................................. 9-6

9-8

Timer Output Compare Block Diagram ............................................................ 9-7

9-9

Output Compare Registers (OCRH, OCRL) .................................................... 9-7

9-10

Timer Control Register (TCR) .......................................................................... 9-8

9-11

Timer Status Registers (TSR) .......................................................................... 9-9

10-1

USB Block Diagram ....................................................................................... 10-2

10-2

Supported Transaction Types per Endpoint................................................... 10-3

10-3

Supported USB Packet Types ....................................................................... 10-4

10-4

Sync Pattern................................................................................................... 10-4

10-5

SOP, Sync Signaling and Voltage Levels ...................................................... 10-5

10-6

CRC Block Diagram for Address and Endpoint Fields................................... 10-6

10-7

CRC Block Diagram for Data Packets ........................................................... 10-7

10-8

EOP Transaction Voltage Levels ................................................................... 10-8

10-9

EOP Width Timing.......................................................................................... 10-8

10-10 External Low Speed Device Configuration................................................... 10-10

10-11 Regulator Electrical Connections ................................................................. 10-11

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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