HC705JB2GRSSLASHH datasheet(78/128 Pages) NXP

78 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

UNIVERSAL SERIAL BUS MODULE

MC68HC705JB2

10-10

REV 1.1

10.2.4.2 USB Reset Signalling

Reset can wake a device from the suspended mode. A device may take up to 10

ms to wake up from the suspended state.

10.2.4.3 Remote Wake-up

The MC68HC705JB2 also supports the remote wake-up feature. The ﬁrmware

has the ability to exit suspend mode by signaling a resume state to the upstream

Host or Hub. A non-idle state (“K” state) on the USB data lines is accomplished by

asserting the FRESUM bit in the UCR1 register.

When using the remote wake-up capability, the ﬁrmware must wait for at least 5

ms after the bus is in the idle state before sending the remote wake-up resume

signaling. This allows the upstream devices to get into their suspend state and

prepare for propagating resume signaling. The FRESUM bit should be asserted to

cause the resume state on the USB data lines for at least 10ms, but not more than

15ms. Note that the resume signalling is controlled by the FRESUM bit and

meeting the timing speciﬁcations is dependent on the ﬁrmware. When FRESUM is

cleared by ﬁrmware, the data lines will return to their high impedance state. Refer

to Section 10.5.5 for more information about how the Force Resume (FRESUM)

bit can be used to initiate the remote wake-up feature.

10.2.5 Low Speed Device

Externally, low speed devices are conﬁgured by the position of a pull-up resistor

on the USB D- pin of the MC68HC705JB2. Low speed devices are terminated as

shown in Figure 10-10 with the pull-up on the D- line.

Figure 10-10. External Low Speed Device Conﬁguration

For low speed transmissions, the transmitter’s EOP width must be between

1.25

µs and 1.50µs. These ranges include timing variations due to differential

buffer delay and rise/fall time mismatches and to noise and other random effects.

A low speed receiver must accept a 670 ns wide SE0 followed by a J transition as

a valid EOP. An SE0 narrower than 330 ns or an SE0 not followed by a J transition

must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected

or accepted as above. Any SE0 that is 2.5

µs or wider is automatically a reset.

68HC705JB2

1.5K

Ω

D+

D–

3.3V Regulator Out

USB Low Speed Cable

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H 数据表(PDF) 78 Page - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 78 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载