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HC705JB2GRS/H 数据表(PDF) 43 Page - NXP Semiconductors

部件名 HC705JB2GRS/H
功能描述  Industry standard M68HC05 CPU core
PDF  128 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 43 Page - NXP Semiconductors

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August 28, 1998
GENERAL RELEASE SPECIFICATION
LOW POWER MODES
REV 1.1
6-1
SECTION 6
LOW POWER MODES
The MC68HC705JB2 has two low-power operating modes: STOP mode and
WAIT mode.
The STOP and WAIT instructions provide two modes that reduce the power
required for the MCU by stopping various internal clocks and/or the oscillator. The
flow of the STOP, and WAIT modes are shown in Figure 6-1.
6.1
STOP MODE
Execution of the STOP instruction in this mode places the MCU in its lowest
power consumption mode. In the STOP Mode the internal oscillator is turned off,
halting all internal processing.
Execution of the STOP instruction automatically clears the I-bit in the Condition
Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so
that the IRQ external interrupt is enabled. All other registers, including the other
bits in the TCSR, and memory remain unaltered. All input/output lines remain
unchanged.
The MCU can be brought out of the STOP Mode by an IRQ external interrupt or a
USB coming out from Suspend Mode Interrupt (Bus activity detection) or an
externally generated RESET, USB Reset or an LVR reset. When exiting the STOP
Mode the internal oscillator will resume after a 128 or 4064 internal processor
clock cycle oscillator stabilization delay.
6.2
WAIT MODE
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Execution of the
WAIT instruction automatically clears the I-bit in the Condition Code Register and
sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ
external interrupt is enabled. All other registers, memory, and input/output lines
remain in their previous states.
The WAIT Mode may be exited when an external IRQ or a USB or Timer1 or MFT
interrupt, an LVR reset or an external RESET occurs.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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