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HC705JB2GRS/H 数据表(PDF) 71 Page - NXP Semiconductors

部件名 HC705JB2GRS/H
功能描述  Industry standard M68HC05 CPU core
PDF  128 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 71 Page - NXP Semiconductors

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August 28, 1998
GENERAL RELEASE SPECIFICATION
UNIVERSAL SERIAL BUS MODULE
REV 1.1
10-3
10.2.1 USB Protocol
Figure 10-2
shows
the
various
transaction
types
supported
by
the
MC68HC705JB2 USB module. The transactions are portrayed as error free. The
effect of errors in the data flow are discussed later.
Figure 10-2. Supported Transaction Types per Endpoint
Each USB transaction is comprised of a series of packets. The MC68HC705JB2
USB module supports the packet types shown in Figure 10-3. Token packets are
generated by the USB host and decoded by the USB device. Data and
Handshake packets are both decoded and generated by the USB device
depending on the type of transaction.
SETUP
IN
OUT
DATA0/1
DATA0
DATA1
ACK
DATA1
OUT
ACK
OUT
DATA0
ACK
ACK
DATA0/1
ENDPOINT 0 TRANSACTIONS:
Control Write
Control Read
No-Data Control
ENDPOINTS 1 & 2 TRANSACTIONS:
Interrupt
Bulk Transmit
IN
ACK
KEY:
Unrelated Bus
Traffic
Host
Generated
Device
Generated
ACK
SETUP
OUT
IN
DATA0/1
DATA0
DATA1
ACK
DATA1
IN
ACK
IN
DATA0
ACK
ACK
ACK
SETUP
IN
DATA0
DATA1
ACK
ACK
DATA0/1
IN
ACK
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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