HC705JB2GRSSLASHH datasheet(64/128 Pages) NXP

64 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

PROGRAMMABLE TIMER

MC68HC705JB2

9-6

REV 1.1

trigger to improve noise immunity. The edge that triggers the counter transfer is

deﬁned by the input edge bit (IEDG) in the TCR. Reset does not affect the

contents of the input capture registers.

The result obtained by an input capture will be one count higher than the value of

the free-running timer counter preceding the external transition. This delay is

required for internal synchronization. Resolution is affected by the prescaler,

allowing the free-running timer counter to increment once every four internal clock

cycles (eight oscillator clock cycles).

Reading the ICRH inhibits further captures until the ICRL is also read. Reading

the ICRL after reading the timer status register (TSR) clears the ICF ﬂag bit. does

not inhibit transfer of the free-running counter. There is no conﬂict between

reading the ICRL and transfers from the free-running timer counters. The input

capture registers always contain the free-running timer counter value which

corresponds to the most recent input capture.

NOTE

To prevent interrupts from occurring between readings of the ICRH

and ICRL, set the I bit in the condition code register (CCR) before

reading ICRH and clear the I bit after reading ICRL.

9.4

OUTPUT COMPARE REGISTERS

The Output Compare function is a means of generating an interrupt when the 16-

bit timer counter reaches a selected value as shown in Figure 9-8. Software

writes the selected value into the output compare registers. On every fourth

internal clock cycle (every eight oscillator clock cycle) the output compare circuitry

compares the value of the free-running timer counter to the value written in the

output compare registers. When a match occurs, the output compare interrupt

ﬂag, OCF is set. A timer interrupt request to the CPU is generated if the output

compare interrupt enable is set, i.e. OCIE=1.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ICRH

ICRH7

ICRH6

ICRH5

ICRH4

ICRH3

ICRH2

ICRH1

ICRH0

$0014

reset:

UUUUUUUU

ICRL

ICRL7

ICRL6

ICRL5

ICRL4

ICRL3

ICRL2

ICRL1

ICRL0

$0015

reset:

UUUUUUUU

U = UNAFFECTED BY RESET

Figure 9-7. Input Capture Registers (ICRH, ICRL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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