HC705JB2GRSSLASHH datasheet(14/128 Pages) NXP

14 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

GENERAL DESCRIPTION

MC68HC705JB2

1-2

REV 1.1

1.2

MASK OPTIONS

The mask options on the MC68HC705JB2 are handled with ﬁve EPROM bits in

the Mask Option Register ($01FF). These options are:

•

External interrupt pins (IRQ, PA0 to PA3):

[edge-triggered or edge-and-level-triggered]

•

Port A and port B pull-down/pull-up resistors:

[connected or disconnected]

•

PA0-PA3 external interrupt capability:

[enabled or disabled]

•

OSC, crystal/ceramic resonator startup delay:

[4064 or 128 internal bus cycles]

•

Low Voltage Reset (LVR):

[enabled or disabled]

To program the MOR, the MORON bit in the Program Control Register

(bit 3 of $3E) must be set to “1”.

IRQTRIG – IRQ, PA0-PA3 Interrupt Options

1 =

Edge-trigger only

0 =

Edge-and-level-triggered

PULLREN – Port A and B Pullup/Pulldown Options

1 =

Connected

0 =

Disconnected

PAINTEN – PA0-PA3 External Interrupt Options

1 =

Disabled

0 =

Enabled

OSCDLY – Oscillator Delay Option

1 =

128 internal clock cycles

0 =

4064 internal clock cycles

LVREN – LVR Option

1 =

Enabled

0 =

Disabled

bit-7

bit-6

bit-5

bit4

bit-3

bit-2

bit1

bit-0

MOR

$01FF

Read

IRQTRIG

PULLREN

PAINTEN

OSCDLY

LVREN

Write

Erased

0001

111

Reset

Unaffected

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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