HC705JB2GRSSLASHH datasheet(34/128 Pages) NXP

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GENERAL RELEASE SPECIFICATION

August 28, 1998

INTERRUPTS

MC68HC705JB2

4-4

REV 1.1

4.3

SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is

executed regardless of the state of the I-bit in the CCR. As with any instruction,

interrupts pending during the previous instruction will be serviced before the SWI

opcode is fetched. The interrupt service routine address is speciﬁed by the

contents of memory locations $1FFC and $1FFD.

4.4

HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the

I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing

the I-bit enables the hardware interrupts. There are two types of hardware

interrupts which are explained in the following sections.

4.4.1 External Interrupt (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of

the IRQ function is shown in Figure 4-2.

Figure 4-2. External Interrupt (IRQ) Logic

IRQ

LATCH

VDD

RST

IRQ VECTOR FETCH

IRQ STATUS/CONTROL REGISTER

EXTERNAL

INTERRUPT

REQUEST

INTERNAL DATA BUS

TO BIH & BIL

INSTRUCTION

PROCESSING

IRQ Level

(Mask Option)

PA0

PA1

PA2

PA3

Port A External Interrupt

(Mask Option)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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