HC705JB2GRSSLASHH datasheet(10/128 Pages) NXP

10 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

MC68HC705JB2

viii

REV 1.1

LIST OF FIGURES

Figure

Title

Page

10-12 Low Speed Driver Signal Waveforms .......................................................... 10-12

10-13 Differential Input Sensitivity Over Entire Common Mode Range ................. 10-13

10-14 Data Jitter..................................................................................................... 10-14

10-15 Data Signal Rise and Fall Time.................................................................... 10-14

10-16 NRZI Data Encoding .................................................................................... 10-16

10-17 Flow Diagram for NRZI ................................................................................ 10-16

10-18 Bit Stuffing.................................................................................................... 10-16

10-19 Flow Diagram for Bit Stuffing ....................................................................... 10-17

10-20 USB Address Register (UADDR) ................................................................. 10-19

10-21 USB Interrupt Register 0 (UIR0) .................................................................. 10-19

10-22 USB Interrupt Register 1(UIR1) ................................................................... 10-20

10-23 USB Control Register 0 (UCR0)................................................................... 10-22

10-24 USB Control Register 1 (UCR1)................................................................... 10-23

10-25 USB Control Register 2 (UCR2)................................................................... 10-24

10-26 USB Status Register (USR) ......................................................................... 10-25

10-27 USB Endpoint 0 Data Register (UE0D0-UE0D7)......................................... 10-26

10-28 USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)...................... 10-26

10-29 OUT Token Data Flow for Receive Endpoint 0 ............................................ 10-29

10-30 SETUP Token Data Flow for Receive Endpoint 0........................................ 10-30

10-31 IN Token Data Flow for Transmit Endpoint 0 ............................................... 10-31

10-32 IN Token Data Flow for Transmit Endpoint 1/ Endpoint 2............................ 10-32

11-1

EPROM Programming Sequence .................................................................. 11-3

14-1

20-Pin PDIP Mechanical Dimensions ............................................................ 14-1

14-2

20-Pin SOIC Mechanical Dimensions ............................................................ 14-2

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H 数据表(PDF) 10 Page - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 10 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载