HC705JB2GRSSLASHH datasheet(91/128 Pages) NXP

91 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

UNIVERSAL SERIAL BUS MODULE

REV 1.1

10-23

TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size

These read/write bits store the number of transmit data bytes for the next IN

token request for Endpoint 0. These bits are cleared by reset.

10.5.5 USB Control Register 1 (UCR1)

T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit

This read/write bit determines which type of data packet (DATA0 or DATA1) will

be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.

Toggling of this bit must be controlled by software. Reset clears this bit.

1 =

DATA1 Token active for next Endpoint 1/Endpoint 2 transmit

0 =

DATA0 Token active for next Endpoint 1/Endpoint 2 transmit

ENDADD — Endpoint Address Select

This read/write bit speciﬁes whether the data inside the registers UE1D0-

UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a

successful Endpoint 2 USB response to a hosts IN token are satisﬁed

(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit

is conﬁgured for Endpoint 1, the USB responds with a NAK handshake packet.

1 =

The data buffers are used for Endpoint 2

0 =

The data buffers are used for Endpoint 1

TX1E — Endpoint 1/Endpoint 2 Transmit Enable

This read/write bit enables a transmit to occur when the USB Host controller

sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint

enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.

Software should set the TX1E bit when data is ready to be transmitted. It must

be cleared by software when no more data needs to be transmitted.

If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake

to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.

1 =

Data is ready to be sent.

0 =

Data is not ready. Respond with NAK.

FRESUM — Force Resume

This read/write bit forces a resume state (“K” or non-idle state) onto the USB

data lines to initiate a remote wake-up. Software should control the timing of the

forced resume to be between 10ms and 15 ms. Setting this bit will not cause

the RESUMF bit to set.

1 =

Force data lines to “K” state

0 =

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UCR1

T1SEQ

ENDADD

TX1E

FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0

$003C

reset

⇒

00000000

Figure 10-24. USB Control Register 1 (UCR1)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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