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HC705JB2GRS/H 数据表(PDF) 37 Page - NXP Semiconductors

部件名 HC705JB2GRS/H
功能描述  Industry standard M68HC05 CPU core
PDF  128 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 37 Page - NXP Semiconductors

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August 28, 1998
GENERAL RELEASE SPECIFICATION
INTERRUPTS
REV 1.1
4-7
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ
pin itself, and not to the output of the logic OR function with the PA0
thru PA3 pins. The state of the individual Port A pins can be checked
by reading the appropriate Port A pins as inputs.
NOTE
If enabled, the PA0 to PA3 pins will cause an IRQ interrupt
regardless of whether these pins are configured as inputs or
outputs.
4.4.4 Timer1 Interrupt (TIMER1)
The TIMER interrupt is generated by the timer when either a timer1 overflow or a
input capture or output compare has occurred as described in Section 9. The
interrupt flags and enable bits for the Timer1 interrupts are located in the Timer1
Control & Status Register (TSR) located at $0012, $0013. The I-bit in the CCR
must be clear in order for the TIMER1 interrupt to be enabled. Either of these
three interrupts will vector to the same interrupt service routine located at the
address specified by the contents of memory locations $1FF6 and $1FF7.
4.4.5 USB Interrupt (USB)
The USB interrupt is generated by the USB module as described in Section 10.
The interrupt enable bits for the USB interrupt are located at bit3-bit2 of UIR0
REG and bit3-bit2 of UIR1 REG. Also Once the device goes into Suspend Mode,
any bus activities will cause the USB to generate an interrupt to CPU to come out
from the Suspend mode. The I-bit in the CCR must be clear in order for the USB
interrupt to be enabled. Either of these two interrupts will vector to the same
interrupt service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
4.4.6 MFT Interrupt (MFT)
The MFT interrupt is generated by the MFT module as described in Section 8.
These interrupts will vector to the same interrupt service routine located at the
address specified by the contents of memory locations $1FF4 and $1FF5.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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