HC705JB2GRSSLASHH datasheet(68/128 Pages) NXP

68 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

PROGRAMMABLE TIMER

MC68HC705JB2

9-10

REV 1.1

OCF - OUTPUT COMPARE FLAG

The OCF bit is automatically set when the value of the timer registers matches

the contents of the output compare registers. Clear the OCF bit by reading the

timer status register with the OCF set, and then accessing the low byte (OCRL,

$0017) of the output compare registers. Reset has no effect on OCF.

TOF - TIMER OVERFLOW FLAG

The TOF bit is automatically set when the 16-bit timer counter rolls over from

$FFFF to $0000. Clear the TOF bit by reading the timer status register with the

TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.

Reset has no effect on TOF.

9.7

TIMER OPERATION DURING WAIT MODE

During WAIT mode the 16-bit timer continues to operate normally and may

generate an interrupt to trigger the MCU out of the WAIT mode.

9.8

TIMER OPERATION DURING STOP MODE

When the MCU enters the STOP mode the free-running counter stops counting

(the internal processor clock is stopped). It remains at that particular count value

until the STOP mode is exited by applying a low signal to the IRQ pin, at which

time the counter resumes from its stopped value as if nothing had happened. If

STOP mode is exited via an external reset (logic low applied to the RESET pin)

the counter is forced to $FFFC.

If a valid input capture edge occurs at the PB0/TCAP pin during the STOP mode

the input capture detect circuitry will be armed. This action does not set any ﬂags

or “wake up” the MCU, but when the MCU does “wake up” there will be an active

input capture ﬂag (and data) from the ﬁrst valid edge. If the STOP mode is exited

by an external reset, no input capture ﬂag or data will be present even if a valid

input capture edge was detected during the STOP mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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