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HC705JB2GRS/H 数据表(PDF) 18 Page - NXP Semiconductors |
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HC705JB2GRS/H 数据表(HTML) 18 Page - NXP Semiconductors |
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18 / 128 page ![]() GENERAL RELEASE SPECIFICATION August 28, 1998 GENERAL DESCRIPTION MC68HC705JB2 1-6 REV 1.1 components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor of 2M Ω (typical) is provided between OSC1 and OSC2 for the ceramic resonator type oscillator. 1.4.2.3 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). 1.4.3 RESET This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to VDD, when the power is removed. An internal pull-up is also connected between this pin and VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. This pin is an output pin if LVR triggers an internal reset. 1.4.4 IRQ/VPP This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. NOTE Each of the PA0 thru PA3 I/O pins may be connected as an OR function with the IRQ interrupt function by a mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ pin, except for the inverted phase. The edge or level sensitivity selected by a separate mask option for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal. In Bootloader mode, this pin (VPP) is used to supply the required programming voltage to the EPROM array. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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