HC705JB2GRSSLASHH datasheet(56/128 Pages) NXP

56 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

MULTI-FUNCTION TIMER

MC68HC705JB2

8-2

REV 1.1

function is implemented on the last stage of this counter, giving a possible

interrupt at the rate of fop/1024. Two additional stages produce the POR function

at fop/4064. The Timer Counter Bypass circuitry (available only in Expanded Test

Mode) is at this point in the timer chain. This circuit is followed by two more

stages, with the resulting clock (fop/16384) driving the Real Time Interrupt circuit.

The RTI circuit consists of three divider stages with a 1 of 4 selector. The RTI rate

selector bits, and the RTI and TOF enable bits and ﬂags are located in the Timer

Control and Status Register at location $08.

The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4

selector. The clock frequency that drives the RTI circuit is fop/2

14 (or f

op/16384)

with three additional divider stages giving a maximum interrupt period of fop/2

(or fop/131072).

The power-on cycle clears the entire counter chain and begins clocking the

counter. After 128 or 4064 cycles, the power-on reset circuit is released which

again clears the counter chain and allows the device to come out of reset. At this

point, if RESET is not asserted, the timer will start counting up from zero and

normal device operation will begin. If RESET is asserted at any time during

operation the counter chain will be cleared.

8.1

TIMER REGISTERS

The 15-stage Multi-function Timer contains two registers: a Timer Counter

8.1.1 Timer Counter Register (TCNT) $09

The Timer Counter Register is a read-only register which contains the current

value of the 8-bit ripple counter at the beginning of the timer chain. This counter is

clocked at fop divided by 4 and can be used for various functions including a

software input capture. Extended time periods can be attained using the TOF

function to increment a temporary RAM storage location thereby simulating a 16-

bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2.

This register is cleared by reset.

Figure 8-2. Timer Counter Register

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TCNT

TMR7

TMR6

TMR5

TMR4

TMR3

TMR2

TMR1

TMR0

$0009

reset:

00000000

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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