HC705JB2GRSSLASHH datasheet(51/128 Pages) NXP

51 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

REV 1.1

7-5

7.2.2 Port B Data Direction Register

Port B I/O pins may be programmed as an input by clearing the corresponding bit

in the DDRB, or programmed as an output by setting the corresponding bit in the

DDRB. The DDRB can be accessed at address $0005. Unused bits will always

read as logic zeros, and any write to these bits will be ignored. The DDRB is

cleared by reset.

If conﬁgured as output pins, PB1 and PB2 have slow output falling-edge transition

feature. The slow transition feature is controlled by the SLOWE bit of DDRB.

SLOWE bit, if set and if the pin is conﬁgured as an output pin, enables the slow

falling-edge output transition feature of PB1 and PB2.

7.2.3 Slow Output Falling-Edge Transition

SLOWE - Slow Transition Enable

The slow transition feature is controlled by the SLOWE bit of DDRB (Port B

Data Direction Register). Default value of SLOWE bit is clear on reset.

1 =

Enables the slow falling-edge output transition feature on both PB1

and PB2, if the pin is conﬁgured as an output pin. PB2 falling edge

transition is a sharp falling edge transition delayed by tCYC/2 after

the write cycle to PB2 data register. PB1 is a true slow transition I/O

line.

0 =

Disables slow falling-edge output transition feature on both PB1 and

PB2.

7.2.4 Port B Pulldown/Pullup Register

All Port B I/O pins may have software programmable pulldown/pullup devices

enabled by a mask option. If the pulldown/pullup mask option is selected, the

pulldown/pullup is activated whenever the corresponding bit in the PDURB is

clear. A pulldown on an I/O pin is activated only if the I/O pin is programmed as an

input; whereas a pullup device on an I/O pin is always activated whenever

enabled, regardless of port direction.

The PDURB is a write-only register. Any reads of location $0011 will return

undeﬁned results. Since reset clears both the DDRB and the PDURB, all pins will

initialize as inputs with the pulldown devices active and pullup devices active (if

chosen via mask option).

Typical value of PB1 and PB2 pullup is 100K

Ω (typical).

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DDRB

SLOWE

DDRB2

DDRB1

DDRB0

$0005

reset:

00000000

Figure 7-3. Port B Data Direction Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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