HC705JB2GRSSLASHH datasheet(36/128 Pages) NXP

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GENERAL RELEASE SPECIFICATION

August 28, 1998

INTERRUPTS

MC68HC705JB2

4-6

REV 1.1

IRQR - IRQ Interrupt Acknowledge

The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.

The IRQR acknowledge bit will always read as a logic zero.

1 =

Writing a logic one to the IRQR acknowledge bit will clear the IRQ

latch.

0 =

Writing a logic zero to the IRQR acknowledge bit will have no effect

on the IRQ latch.

IRQF - IRQ Interrupt Request Flag

Writing to the IRQF ﬂag bit will have no effect on it. If the additional setting of

IRQF ﬂag bit is not cleared in the IRQ service routine and the IRQE enable bit

remains set the CPU will re-enter the IRQ interrupt sequence continuously until

either the IRQF ﬂag bit or the IRQE enable bit is clear. The IRQF latch is

cleared by reset.

1 =

Indicates that an IRQ request is pending.

0 =

Indicates that no IRQ request triggered by pins PA0-3 or IRQ is

pending. The IRQF ﬂag bit is cleared once the IRQ vector is fetched.

The IRQF ﬂag bit can be cleared by writing a logic one to the IRQR

acknowledge bit to clear the IRQ latch and also conditioning the

external IRQ sources to be inactive (if the level sensitive interrupts

are enabled via mask option). Doing so before exiting the service

routine will mask out additional occurrences of the IRQF.

IRQE - IRQ Interrupt Enable

The IRQE bit enables/disables the IRQF ﬂag bit to initiate an IRQ interrupt

sequence.

1 =

Enables IRQF interrupt, that is, the IRQF ﬂag bit can generate an

interrupt sequence. Reset sets the IRQE enable bit, thereby

enabling IRQ interrupts once the I-bit is cleared. Execution of the

STOP or WAIT instructions causes the IRQE bit to be set in order to

allow the external IRQ to exit these modes.

0 =

The IRQF ﬂag bit cannot generate an interrupt sequence.

4.4.3 Optional External Interrupts (PA0-PA3)

The IRQ interrupt can also be triggered by the inputs on the PA0 thru PA3 port

pins if enabled by a single mask option. If enabled, the lower four bits of Port A

can activate the IRQ interrupt function, and the interrupt operation will be the

same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of

these input pins to be OR’ed with the input present on the IRQ pin. All PA0 thru

PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3

interrupt sources are also controlled by the IRQE enable bit.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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