HC705JB2GRSSLASHH datasheet(19/128 Pages) NXP

19 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

GENERAL DESCRIPTION

REV 1.1

1-7

1.4.5 PA0-PA7

These eight I/O lines comprise PortA. PA0 to PA7 are push-pull pins with pulldown

devices. PA4 to PA7 are also capable of sinking 8 mA.

The state of any pin is software programmable and all Port A lines are conﬁgured

as inputs during power-on or reset. The lower four I/O pins (PA0 thru PA3) can be

connected via an internal OR gate to the IRQ interrupt function enabled by a mask

option. See Section 7 on Input/Output Ports for further details.

1.4.6 PB0-PB2

These three I/O lines comprise Port B. PB1 and PB2 are open-drain I/O lines with

pullup devices, whereas PB0 (shared with TCAP), is a push-pull I/O line with

pulldown device.

The state of any pin is software programmable and is conﬁgured as an input

during power-on or reset. PB1 and PB2 are also slow transition outputs, each

capable of sinking 25mA typical current at 0.5V VOL Max. See Section 7 on

Input/Output Ports for further details.

1.4.7 D+, D–

D+ and D– are the differential data lines used by the USB module. See

Section 10 on Universal Serial Bus Module.

1.4.8 3.3V

This is the 3.3V output of the on-chip voltage regulator from the MCU. It is used to

supply the voltage for the external pullup resistor required by the USB on D–. This

regulator output is also used internally for the USB data driver circuitry. This 3.3V

pin should be decoupled using a 1

µF (or greater) capacitor and a 0.1µF bypass

capacitor.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H 数据表(PDF) 19 Page - NXP Semiconductors