HC705JB2GRSSLASHH datasheet(67/128 Pages) NXP

67 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

PROGRAMMABLE TIMER

REV 1.1

9-9

OCIE - OUTPUT COMPARE INTERRUPT ENABLE

This read/write bit enables interrupts caused by a successful compare between

the timer counter and the output compare registers. Reset clears the OCIE bit.

1 =

Output compare interrupts enabled.

0 =

Output compare interrupts disabled.

TOIE - TIMER OVERFLOW INTERRUPT ENABLE

This read/write bit enables interrupts caused by a timer overﬂow. Reset clears

the TOIE bit.

1 =

Timer overﬂow interrupts enabled.

0 =

Timer overﬂow interrupts disabled.

IEDG - INPUT CAPTURE EDGE SELECT

The state of this read/write bit determines whether a positive or negative

transition on the TCAP pin triggers a transfer of the contents of the timer

1 =

Positive edge (low to high transition) triggers input capture.

0 =

Negative edge (high to low transition) triggers input capture.

9.6

TIMER STATUS REGISTER (TSR)

The timer status register (TSR) shown in Figure 9-11 contains ﬂags for the

following events:

•

An active signal on the PB0/TCAP pin, transferring the contents of the

timer registers to the input capture registers.

•

A match between the 16-bit counter and the output compare registers

•

An overﬂow of the timer registers from $FFFF to $0000.

Writing to any of the bits in the TSR has no effect. Reset does not change the

state of any of the ﬂag bits in the TSR.

ICF - INPUT CAPTURE FLAG

The ICF bit is automatically set when an edge of the selected polarity occurs on

the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with

the ICF set, and then reading the low byte (ICRL, $0015) of the input capture

registers. Reset has no effect on ICF.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TSR

ICF

OCF

TOF

00000

$0013

reset:

00000

U = UNAFFECTED BY RESET

Figure 9-11. Timer Status Registers (TSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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