HC705JB2GRSSLASHH datasheet(95/128 Pages) NXP

95 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

UNIVERSAL SERIAL BUS MODULE

REV 1.1

10-27

10.6

USB INTERRUPTS

The USB module is capable of generating interrupts and causing the CPU to

execute the USB interrupt service routine. There are three types of USB

interrupts:

•

End of Transaction interrupts signify a completed transaction (receive or

transmit)

•

Resume interrupts signify that the USB bus is reactivated after having

been suspended

•

End of Packet interrupts signify that a low speed end of packet signal

was detected

All USB interrupts share the same interrupt vector. Firmware is responsible for

determining which interrupt is active.

10.6.1 USB End of Transaction Interrupt

There are three possible end of transaction interrupts: Endpoint 0 Receive,

Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of

transaction interrupts occur as detailed in the following sections.

10.6.1.1 Receive Control Endpoint 0

For a Control OUT transaction directed at Endpoint 0, the USB module will

generate an interrupt by setting the RXD0F ﬂag in the UIR0 register. The

conditions necessary for the interrupt to occur are shown in the ﬂowchart of

Figure 10-29.

SETUP transactions cannot be stalled by the USB function. A SETUP received by

a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving

a SETUP interrupt are shown in Figure 10-30.

10.6.1.2 Transmit Control Endpoint 0

For a Control IN transaction directed at Endpoint 0, the USB module will generate

an interrupt by setting the TXD0F ﬂag in the UIR0 register. The conditions

necessary for the interrupt to occur are shown in the ﬂowchart of Figure 10-31.

10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2

Transmit Endpoints 1 & 2 share their interrupt ﬂag. For an IN transaction directed

at Endpoint 1 or 2, the USB module will generate an interrupt by setting the

TXD1F ﬂag in the UIR1 register. The conditions necessary for the interrupt to

occur are shown in the ﬂowchart of Figure 10-32.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H 数据表(PDF) 95 Page - NXP Semiconductors

HC705JB2GRS/H 数据表(HTML) 95 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载