HC705JB2GRSSLASHH datasheet(63/128 Pages) NXP

63 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

PROGRAMMABLE TIMER

REV 1.1

9-5

NOTE

To prevent interrupts from occurring between readings of the ACRH

and ACRL, set the I bit in the condition code register (CCR) before

reading ACRH and clear the I bit after reading ACRL.

9.3

INPUT CAPTURE REGISTERS

The input capture function is a technique whereby an external signal (connected

to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is

possible to relate the timing of an external signal to the internal counter value, and

hence to elapsed time.

When the input capture circuitry detects an active edge on the TCAP pin, it

latches the contents of the free-running timer counter registers into the input

capture registers as shown in Figure 9-6.

Latching values into the input capture registers at successive edges of the same

polarity measures the period of the selected input signal. Latching the counter

values at successive edges of opposite polarity measures the pulse width of the

signal.

Figure 9-6. Timer Input Capture Block Diagram

The input capture registers are made up of two 8-bit read-only registers (ICRH,

ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt

ICRH ($0014)

16-BIT COUNTER

÷ 4

INTERNAL

(fOSC ÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

INPUT CAPTURE (ICF)

RESET

CLOCK

INTERRUPT

ICRL ($0015)

TIMER STATUS REG.

$0012

$0013

INTERNAL

DATA

READ

ICRH

READ

ICRL

LATCH

BUS

EDGE

SELECT

& DETECT

LOGIC

PB0/TCAP

INTERNAL

DATA

BUS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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