HC705JB2GRSSLASHH datasheet(53/128 Pages) NXP

53 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

INPUT/OUTPUT PORTS

REV 1.1

7-7

7.3.4 I/O Pin Transitions

A "glitch" can be generated on an I/O pin when changing it from an input to an

output unless the data register is ﬁrst preconditioned to the desired state before

changing the corresponding DDR bit from a zero to a one.

If pulldowns are enabled by mask option, a ﬂoating input can be avoided by

clearing the pulldown/pullup register bit before changing the corresponding DDR

from a one to a zero. This will insure that the pulldown device will be activated

before the I/O pin changes from a driven output to a pulled low/high input.

7.3.5 I/O Pin Truth Tables

Every pin on Port A and Port B may be programmed as an input or an output

under software control as shown in Table 7-1 and Table 7-2. All port I/O pins may

also have software programmable pulldown/pullup devices if selected by the

appropriate mask option.

Table 7-1. Port A I/O Pin Functions

Table 7-2. Port B I/O Pin Functions

Accesses to

PDURA

at $0010

Accesses to

Data Register

@ $0000

IN, Hi-Z

OUT

PDURA0-7

DDRA0-7

I/O Pin

PA0-7

I/O Pin Mode

DDRA

Read/Write

Accesses

to DDRA

@ $0004

Read

Write

NOTE:

U is undefined.

Read

Write

* Does not affect input,

but stored to data register

Accesses to

PDURB

at $0011

Accesses to

Data Register

@ $0001

IN, Hi-Z

OUT

PDURB0-2

DDRB0-2

I/O Pin

PB0-2

I/O Pin Mode

DDRA

Read/Write

Accesses

to DDRB

@ $0005

Read

Write

Read

Write

* Does not affect input,

but stored to data register

NOTE:

U is undefined.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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