HC705JJ7GRSSLASHD datasheet(136/230 Pages) NXP

136 / 230 page

Analog Subsystem

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Analog Subsystem

be measured, but the logic state of the port B pins can be read from

location $0002.

8.14 Port B Pulldowns

All the port B pins have internal software programmable pulldown

devices available dependent on the state of the SWPDI bit in the mask

option register (MOR).

If the pulldowns are enabled, they will create an approximate 100

µA

load to any analog source connected to the pin. In some cases, the

analog source may be able to supply this current without causing any

error due to the analog source output impedance. Since this may not

always be true, it is therefore best to disable port B pulldowns on those

pins used for analog input sources.

8.15 Noise Sensitivity

In addition to the normal effects of electrical noise on the analog input

signal there can also be other noise related effects caused by the digital-

to-analog interface. Since there is only one VSS return for both the digital

and the analog subsystems on the device, currents in the digital section

may affect the analog ground reference within the device. This can add

voltage offsets to measured inputs or cause channel-to-channel

crosstalk.

In order to reduce the impact of these effects, there should be no

switching of heavy I/O currents to or from the device while there is a

critical analog conversion or voltage comparison in process. Limiting

switched I/O currents to 2–4 mA during these times is recommended.

A noise reduction benefit can be gained with 0.1

µF bypass capacitors

from each analog input (PB4:1) to the VSS pin. Also, try to keep all the

digital power supply or load currents from passing through any

conductors which are the return paths for an analog signal.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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