HC705JJ7GRSSLASHD datasheet(140/230 Pages) NXP

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Simple Serial Interface

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Simple Serial Interface

Figure 9-3. SIOP Timing Diagram (CPHA = 1)

9.3.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is

enabled. New data is presented to the SDI pin on the falling edge of

SCK. Valid data must be present at least 100 nanoseconds before the

rising edge of SCK and remain valid for 100 nanoseconds after the rising

edge of SCK. See Figure 9-3.

9.3.3 Serial Data Output (SDO)

The SDO pin becomes an output as soon as the SIOP subsystem is

enabled. The state of the PB5/SDO pin reflects the value of the first bit

received on the previous transmission. Prior to enabling the SIOP, the

PB5/SDO can be initialized to determine the beginning state. While

SIOP is enabled, the port B logic cannot be used as a standard output

since that pin is connected to the last stage of the SIOP serial shift

be transmitted in either the MSB first format or the LSB first format.

The first data bit will be shifted out to the SDO pin on the first falling edge

of the SCK. The remaining data bits will be shifted out to the SDI pin on

subsequent falling edges of SCK. The SDO pin will present valid data at

least 100 nanoseconds before the rising edge of the SCK and remain

valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.

SCK

SDO

SDI

100 ns

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

(CPHA = 1)

(IDLE = 0)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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