HC705JJ7GRSSLASHD datasheet(141/230 Pages) NXP

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Simple Serial Interface

SIOP Registers

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Simple Serial Interface

9.4 SIOP Registers

The SIOP is programmed and controlled by the SIOP control register

(SCR) located at address $000A, the SIOP status register (SSR) located

at address $000B, and the SIOP data register (SDR) located at address

$000C.

9.4.1 SIOP Control Register (SCR)

The SIOP control register (SCR) is located at address $000A and

contains seven control bits and a write-only reset of the interrupt flag.

Figure 9-4 shows the position of each bit in the register and indicates

the value of each bit after reset.

SPIE — Serial Peripheral Interrupt Enable

The SPIE bit enables the SIOP to generate an interrupt whenever the

SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the

state of the SPIF flag bit and will not terminate a serial interrupt once

the interrupt sequence has started. Reset clears the SPIE bit.

1 = Serial interrupt enabled

0 = Serial interrupt disabled

NOTE:

If the SPIE bit is cleared just after the serial interrupt sequence has

started (for instance, the CPU status is being stacked), then the CPU will

be unable to determine the source of the interrupt and will vector to the

reset vector as a default.

$000A

Bit 7

654321

Bit 0

Read:

SPIE

SPE

LSBF

MSTR

CPHA

SPR1

SPR0

Write:

SPIR

Reset:

00000000

Figure 9-4. SIOP Control Register (SCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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