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HC705JJ7GRS/D 数据表(PDF) 138 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 138 Page - NXP Semiconductors

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Simple Serial Interface
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Simple Serial Interface
Figure 9-1. SIOP Block Diagram
PORTB LOGIC
SIOP
INTERRUPT
PB7
SCK
PB6
SDI
PB5
SDO
SIOP
SPE
SPIE
DATA REGISTER
(SDR)
DCOL
SPIF
FORMAT CONTROL
SPIR
8-BIT SHIFT
LSBF
LATCH
S
R
REGISTER
DIN
DOUT
CLK
CLOCK
CONTROL
MSTR
CPHA
SPR1
SPR0
CLOCK
DIVIDER
OSCILL
CLOCK
Q
(LSB OR MSB FIRST)
PORTB LOGIC
PORTB LOGIC
AND
SELECT
INTERNAL HC05 BUS
COMP
ERROR
÷2
$000A
$000B
$000C
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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