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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HC705JJ7GRS/D 数据表(PDF) 188 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 188 Page - NXP Semiconductors |
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188 / 230 page  Instruction Set General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Instruction Set 14.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. 14.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • Inherent • Immediate • Direct • Extended • Indexed, no offset • Indexed, 8-bit offset • Indexed, 16-bit offset • Relative Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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