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DSP56362P 数据表(PDF) 25 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 152 page ![]() Digital Audio Interface (DAX) DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-19 2.10 Digital Audio Interface (DAX) 2.11 Timer Table 2-12 Digital Audio Interface (DAX) Signals Signal Name Type State During Reset Signal Description ACI PD0 Input Input, Output, or Disconnected Disconnected Audio Clock Input—This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs or 512 × Fs, respectively). Port D 0—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. ADO PD1 Output Input, Output, or Disconnected Disconnected Digital Audio Data Output—This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1—When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 5 V tolerant. Table 2-13 Timer Signal Signal Name Type State During Reset Signal Description TIO0 Input or Output Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected it to Vcc through a pull-up resistor in order to ensure a stable logic level at the input. This input is 5 V tolerant. |
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