DSP56362P datasheet(79/152 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-53

144

Serial clock rise/fall time

Master

—

Slave

—

2000

146

SS assertion to first SCK edge CPHA = 0

Slave

Bypassed

Narrow

Wide

3.5

×T

C+15

—

CPHA = 1

Slave

Bypassed

Narrow

Wide

—

147

Last SCK edge to SS not asserted

slave

Bypassed

Narrow

Wide

102

189

102

189

—

148

Data input valid to SCK edge (data input

set-up time)

Master/

Slave

Bypassed

Narrow

Wide

MAX{(20-TC), 0}

MAX{(40-TC), 0}

—

149

SCK last sampling edge to data input not

valid

Master/

Slave

Bypassed

Narrow

Wide

2.5

×T

C+10

2.5

×T

C+30

2.5

×T

C+50

—

150

SS assertion to data out active

Slave

—

151

SS deassertion to data high impedance

Slave

—

152

SCK edge to data out valid (data out delay

time)

Master/

Slave

Bypassed

Narrow

Wide

×T

C+33

×T

C+123

×T

C+210

—

143

230

153

SCK edge to data out not valid

(data out hold time)

Master/

Slave

Bypassed

Narrow

Wide

TC+5

TC+55

TC+106

116

—

154

SS assertion to data out valid (CPHA = 0)

Slave

—

TC+33

—

157

First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

Narrow

Wide

2.5

×T

C+30

2.5

×T

C+120

2.5

×T

C+217

—

145

242

158

Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

Narrow

Wide

2.5

×T

C+30

2.5

×T

C+80

2.5

×T

C+136

105

161

—

Table 3-21 Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics

Mode

Filter Mode

Expression

100MHz

Unit

Min

Max

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