DSP56362P datasheet(30/152 Pages) FREESCALE

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Internal Clocks

DSP56362 Technical Data, Rev. 4

3-4

Freescale Semiconductor

3.6

Internal Clocks

Table 3-4 Internal Clocks, CLKOUT

Characteristics

Symbol

Expression1

, 2

1 DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL.

Min

Typ

Max

Internal operation frequency and CLKOUT

with PLL enabled

f—

(Ef

× MF)/(PDF × DF)

—

Internal operation frequency and CLKOUT

with PLL disabled

f—

Ef/2

—

Internal clock and CLKOUT high period

• With PLL disabled

•

With PLL enabled and MF

≤ 4

• With PLL enabled and MF > 4

—

0.49

× ET

C × PDF ×

DF/MF

0.47

× ET

C × PDF ×

DF/MF

ETC

—

0.51

× ET

C × PDF ×

DF/MF

0.53

× ET

C × PDF ×

DF/MF

Internal clock and CLKOUT low period

• With PLL disabled

•

With PLL enabled and MF

≤ 4

• With PLL enabled and MF > 4

—

0.49

× ET

C × PDF ×

DF/MF

0.47

× ET

C × PDF ×

DF/MF

ETC

—

0.51

× ET

C × PDF ×

DF/MF

0.53

× ET

C × PDF ×

DF/MF

Internal clock and CLKOUT cycle time with

PLL enabled

—ETC × PDF × DF/MF

—

Internal clock and CLKOUT cycle time with

PLL disabled

—2

× ET

—

Instruction cycle time

ICYC

—TC

—

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