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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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DSP56362P 数据表(PDF) 88 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 152 page  Enhanced Serial Audio Interface Timing DSP56362 Technical Data, Rev. 4 3-62 Freescale Semiconductor 3.14 Enhanced Serial Audio Interface Timing Table 3-24 Enhanced Serial Audio Interface Timing No. Characteristics1 , 2, 3 Symbol Expression 100 MHz Condition4 Unit Min Max 430 Clock cycle5 tSSICC 4 x TC RXC:3 xTC TXC:MAX [3xTC;t454] 40.0 30 40 — — i ck x ck x ck ns 431 Clock high period • For internal clock • For external clock — 2 × TC − 10.0 1.5 × TC 10.0 15.0 — — ns 432 Clock low period • For internal clock • For external clock — 2 × T C − 10.0 1.5 × T C 10.0 15.0 — — ns 433 RXC rising edge to FSR out (bl) high — — — 37.0 x ck ns —22.0 i ck a 434 RXC rising edge to FSR out (bl) low — — — — 37.0 22.0 x ck i ck a ns 435 RXC rising edge to FSR out (wr) high6 —— — — 39.0 24.0 x ck i ck a ns 436 RXC rising edge to FSR out (wr) low6 —— — 39.0 24.0 x ck i ck a ns 437 RXC rising edge to FSR out (wl) high — — — — 36.0 21.0 x ck i ck a ns 438 RXC rising edge to FSR out (wl) low — — — — 37.0 22.0 x ck i ck a ns 439 Data in setup time before RXC (TXC in synchronous mode) falling edge —— 0.0 19.0 — — x ck i ck ns 440 Data in hold time after RXC falling edge — — 5.0 3.0 — — x ck i ck ns 441 FSR input (bl, wr) high before RXC falling edge6 —— 23.0 1.0 — — x ck i ck a ns 442 FSR input (wl) high before RXC falling edge — — 1.0 23.0 — — x ck i ck a ns |
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