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DSP56362P 数据表(PDF) 60 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-34 Freescale Semiconductor 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 0.0 — 0.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × T C − 4.0 58.5 — 48.1 — ns 163 RAS assertion pulse width tRAS 9.75 × T C − 4.0 93.5 — 77.2 — ns 164 CAS assertion to RAS deassertion tRSH 6.25 × T C − 4.0 58.5 — 48.1 — ns 165 RAS assertion to CAS deassertion tCSH 8.25 × T C − 4.0 78.5 — 64.7 — ns 166 CAS assertion pulse width tCAS 4.75 × T C − 4.0 43.5 — 35.6 — ns 167 RAS assertion to CAS assertion tRCD 3.5 × T C ± 2 33.0 37.0 27.2 31.2 ns 168 RAS assertion to column address valid tRAD 2.75 × T C ± 2 25.5 29.5 20.9 24.9 ns 169 CAS deassertion to RAS assertion tCRP 7.75 × T C − 4.0 73.5 — 60.6 — ns 170 CAS deassertion pulse width tCP 6.25 × T C − 4.0 58.5 — 48.1 — ns 171 Row address valid to RAS assertion tASR 6.25 × T C − 4.0 58.5 — 48.1 — ns 172 RAS assertion to row address not valid tRAH 2.75 × T C − 4.0 23.5 — 18.9 — ns 173 Column address valid to CAS assertion tASC 0.75 × T C − 4.0 3.5 — 2.2 — ns 174 CAS assertion to column address not valid tCAH 6.25 × T C − 4.0 58.5 — 48.1 — ns 175 RAS assertion to column address not valid tAR 9.75 × T C − 4.0 93.5 — 77.2 — ns 176 Column address valid to RAS deassertion tRAL 7 × T C − 4.0 66.0 — 54.3 — ns 177 WR deassertion to CAS assertion tRCS 5 × T C − 3.8 46.2 — 37.9 — ns 178 CAS deassertion to WR4 assertion tRCH 1.75 × T C − 3.7 13.8 — 10.9 — ns 179 RAS deassertion to WR4 assertion tRRH 0.25 × T C − 2.0 0.5 — 0.1 — ns 180 CAS assertion to WR deassertion tWCH 6 × T C − 4.2 55.8 — 45.8 — ns 181 RAS assertion to WR deassertion tWCR 9.5 × T C − 4.2 90.8 — 75.0 — ns 182 WR assertion pulse width tWP 15.5 × T C − 4.5 150.5 — 124.7 — ns 183 WR assertion to RAS deassertion tRWL 15.75 × T C − 4.3 153.2 — 126.9 — ns 184 WR assertion to CAS deassertion tCWL 14.25 × T C − 4.3 138.2 — 114.4 — ns 185 Data valid to CAS assertion (write) tDS 8.75 × T C − 4.0 83.5 — 68.9 — ns Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (continued) No. Characteristics3 Symbol Expression 100 MHz 120 MHz Unit Min Max Min Max |
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