DSP56362P datasheet(11/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

2-5

2.5

External Memory Expansion Port (Port A)

When the DSP56362 enters a low-power standby mode (stop or wait), it releases bus mastership and

tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS.

2.5.1

External Address Bus

2.5.2

External Data Bus

PCAP

Input

PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL

filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP.

If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.

PINIT/NMI

Input

PLL Initial/Non maskable Interrupt—During assertion of RESET, the value of

PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the PLL is enabled or disabled. After RESET deassertion

and during normal instruction processing, the PINIT/NMI Schmitt-trigger input

is a negative-edge-triggered non maskable interrupt (NMI) request internally

synchronized to CLKOUT.

PINIT/NMI cannot tolerate 5 V.

Table 2-5 External Address Bus Signals

Signal Name

Type

State during Reset

Signal Description

A0–A17

Output

Tri-Stated

Address Bus—When the DSP is the bus master, A0–A17 are

active-high outputs that specify the address for external program and

data memory accesses. Otherwise, the signals are tri-stated. To

minimize power dissipation, A0–A17 do not change state when

external memory spaces are not being accessed.

Table 2-6 External Data Bus Signals

Signal Name

Type

State during Reset

Signal Description

D0–D23

Input/Output

Tri-Stated

Data Bus—When the DSP is the bus master, D0–D23 are active-high,

bidirectional input/outputs that provide the bidirectional data bus for

external program and data memory accesses. Otherwise, D0–D23 are

tri-stated.

Table 2-4 Clock and PLL Signals (continued)

Signal Name

Type

State during Reset

Signal Description

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