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DSP56362P 数据表(PDF) 99 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 99 Page - Freescale Semiconductor, Inc |
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99 / 152 page ![]() OnCE Module TimIng DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-73 Figure 3-52 TRST Timing Diagram 3.19 OnCE Module TimIng Figure 3-53 OnCE—Debug Request Table 3-29 OnCE Module Timing1 1 V CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF No. Characteristics Expression 100 MHz Unit Min Max 500 TCK frequency of operation 1/(TC × 3), max 22.0 MHz 0.0 22.0 MHz 514 DE assertion time in order to enter Debug mode 1.5 × T C + 10.0 25.0 — ns 515 Response time when DSP56362 is executing NOP instructions from internal memory 5.5 × T C + 30.0 — 85.0 ns 516 Debug acknowledge assertion time 3 × T C + 10.0 40.0 — ns TCK (Input) TRST (Input) 513 512 AA0499 DE 516 515 514 AA0500 |
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