DSP56362P datasheet(3/152 Pages) FREESCALE

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Overview

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

1-3

1.1

Features

•

Multimode, multichannel decoder software functionality

— Dolby Digital and Pro Logic

— MPEG2 5.1

—DTS

— Bass management

•

Digital audio post-processing capabilities

— 3D Virtual surround sound

— Lucasfilm THX5.1

— Soundfield processing

— Equalization

•

Digital Signal Processing Core

— 100 MIPS with a 100 MHz clock at 3.3 V +/- 5%

— Object code compatible with the DSP56000 core

— Highly parallel instruction set

— Data arithmetic logic unit (ALU)

– Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

– 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

– Conditional ALU instructions

– 24-bit or 16-bit arithmetic support under software control

— Program control unit (PCU)

– Position independent code (PIC) support

– Addressing modes optimized for DSP applications (including immediate offsets)

– On-chip instruction cache controller

– On-chip memory-expandable hardware stack

– Nested hardware DO loops

– Fast auto-return interrupts

— Direct memory access (DMA)

– Six DMA channels supporting internal and external accesses

– One-, two-, and three- dimensional transfers (including circular buffering)

– End-of-block-transfer interrupts

– Triggering from interrupt lines and all peripherals

— Phase-locked loop (PLL)

– Software programmable PLL-based frequency synthesizer for the core clock

– Allows change of low-power divide factor (DF) without loss of lock

– Output clock with skew elimination

— Hardware debugging support

DSP56362P 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

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