DSP56362P datasheet(47/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-21

Table 3-10

DRAM Page Mode Timings, Two Wait States1, 2, 3, 4

No.

Characteristics

Symbol

Expression

80 MHz

Unit

Min

Max

131

Page mode cycle time for two consecutive accesses of the

same direction5

Page mode cycle time for mixed (read and write) accesses.5

tPC

× T

2.75 x Tc

37.5

34.4

—

132

CAS assertion to data valid (read)

tCAC

1.5

× T

C − 6.5

—

12.3

133

Column address valid to data valid (read)

tAA

2.5

× T

C − 6.5

—

24.8

134

CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

135

Last CAS assertion to RAS deassertion

tRSH

1.75

× T

C − 4.0

17.9

—

136

Previous CAS deassertion to RAS deassertion

tRHCP

3.25

× T

C − 4.0

36.6

—

137

CAS assertion pulse width

tCAS

1.5

× T

C − 4.0

14.8

—

138

Last CAS deassertion to RAS deassertion6

• BRW[1:0] = 00

• BRW[1:0] = 01

• BRW[1:0] = 10

• BRW[1:0] = 11

tCRP

2.0

× T

C − 6.0

3.5

× T

C − 6.0

4.5

× T

C − 6.0

6.5

× T

C − 6.0

19.0

37.8

50.3

75.3

—

139

CAS deassertion pulse width

tCP

1.25

× T

C − 4.0

11.6

—

140

Column address valid to CAS assertion

tASC

TC − 4.0

8.5

—

141

CAS assertion to column address not valid

tCAH

1.75

× T

C − 4.0

17.9

—

142

Last column address valid to RAS deassertion

tRAL

× T

C − 4.0

33.5

—

143

WR deassertion to CAS assertion

tRCS

1.25

× T

C − 3.8

11.8

—

144

CAS deassertion to WR assertion

tRCH

0.5

× T

C − 3.7

2.6

—

145

CAS assertion to WR deassertion

tWCH

1.5

× T

C − 4.2

14.6

—

146

WR assertion pulse width

tWP

2.5

× T

C − 4.5

26.8

—

147

Last WR assertion to RAS deassertion

tRWL

2.75

× T

C − 4.3

30.1

—

148

WR assertion to CAS deassertion

tCWL

2.5

× T

C − 4.3

27.0

—

149

Data valid to CAS assertion (write)

tDS

0.25

× T

C − 3.0

0.1

—

150

CAS assertion to data not valid (write)

tDH

1.75

× T

C − 4.0

17.9

—

151

WR assertion to CAS assertion

tWCS

TC − 4.3

8.2

—

152

Last RD assertion to RAS deassertion

tROH

2.5

× T

C − 4.0

27.3

—

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